This application is related to Korean Application No. 2000-64218, filed Oct. 31, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to semiconductor devices and, more particularly, to semiconductor devices that improve stability and amplification in semiconductor memory devices.
Voltage sense amplifiers and/or current sense amplifiers are typically used to output data in semiconductor memory devices. Current sense amplifiers may be used more often because they may provide faster sensing speeds. A current sense amplifier typically receives current on a pair of input lines, amplifies the current as a voltage signal and outputs the amplified signal. The current sense amplifier uses a positive feedback circuit to provide an accurate current. These conventional current sense amplifiers may cause instability in the semiconductor device, such as oscillation of an output voltage.
Referring to FIG. 1, a detailed circuit diagram of conventional current sense amplifier circuits having a positive feedback circuit will be described. The current sense amplifier circuit consists of PMOS transistors MP11 and MP12 for sensing a current, NMOS transistors MN11 and MN12 for acting as a load resistance, and a switching transistor MN13. Currents I1 and I2 received over a pair of differential input/output lines IO and IOB (not shown) are input to input terminals IN and INB. PMOS transistors MP11 and MP12 are connected in a latch structure, i.e. the gates and drains of PMOS transistors MP11 and MP12 are cross coupled, and the drains of the PMOS transistors MP11 and MP12 are connected to an output terminal OUT and a complementary output terminal OUTB, respectively. The NMOS transistors MN11 and MN12 may be formed of diode-type transistors and may have the same resistance values. The switching transistor MN13 is switched by an enable signal and allows the predetermined currents I1 and I2 supplied from the pair of differential input/output lines IO and IOB (not shown) to be directed to a ground voltage VSS.
It will be understood that in conventional current sense amplifiers, for example, the current sense amplifier of FIG. 1, it may be difficult to maintain and/or improve stability and amplification of the semiconductor device while effectively sensing the current of the semiconductor device. For example, in the case of the PMOS transistors MP11 and MP12, a current difference xcex94I may be obtained using the following equations:
I1=xe2x88x92gmp*voutbxe2x80x83xe2x80x83(1)
I2=xe2x88x92gmp*voutxe2x80x83xe2x80x83(2)
xcex94I=I1xe2x88x922=gmp(voutxe2x88x92voutb)xe2x80x83xe2x80x83(3)
where I1 and I2 represent predetermined currents supplied from the pair of differential input/output lines IO and IOB, respectively, gmp represents the transconductance of PMOS transistors MP11 and MP12, vout represents the output voltage of output terminal OUT, voutb represents the output voltage of complementary output terminal OUTB, and xcex94I represents the difference between first and second currents I1 and I2, respectively.
Furthermore, in the case of NMOS transistors MN11 and MN12, a current difference xcex94I may be obtained using the following equations:
I1=gmn*voutxe2x80x83xe2x80x83(4)
I2=gmn*voutbxe2x80x83xe2x80x83(5)
xcex94I=I1xe2x88x92I2=gmn (voutvoutb)xe2x80x83xe2x80x83(6)
where I1 and I2 represent predetermined currents supplied from the pair of differential input/output lines IO and IOB, respectively, gmn represents the transconductance of NMOS transistors MN11 and MN12, vout represents the output voltage of output terminal OUT, voutb represents the output voltage of complementary output terminal OUTB, and xcex94I represents the difference between first and second currents I1 and I2.
Typically, the voltages and currents of NMOS transistors MN11 and MN12 and PMOS transistors MP11 and MP12 are the same, thus, gmp is typically equal to gmn. However, when gmp is larger than gmn, PMOS transistors MP11 and MP12 may amplify a larger current difference than the original current difference xcex94I, thus, reversing the voltages of the input terminals IN and INB. This may cause the voltages and currents of PMOS transistors MP11 and MP12 to be unstable. Thus, with respect to maintaining stability of the semiconductor device, gmn is preferably larger than gmp. On the other hand, when gmn is larger than gmp the current sense amplifier circuit may be less efficient and this may cause the sensing speed of the semiconductor device to deteriorate. Thus, a trade-off exists between stability of the semiconductor device and sensing speed of the semiconductor device and the transconductances gmn and gmp should be chosen accordingly. The modulation effects of a PMOS channel length is typically larger than the modulation effects of an NMOS channel length, thus, the larger a power supply voltage, the larger the transconductance gmp of the PMOS transistors MP11 and MP12.
Now referring to FIG. 2, a diagram illustrating the current and/or voltage characteristics of transistors in conventional current sense amplifier circuits, for example, as shown in FIG. 1, will be described. Voltages Vgsn and Vgsp between the gates and the sources of the NMOS transistors and the PMOS transistors are illustrated on the horizontal axis, and the drain currents Idn and Idp of each of the NMOS and PMOS transistors are illustrated on the vertical axis. As illustrated, when the voltages Vgsn and Vgsp are larger than a predetermined voltage Vc, the slope of a curve of current and/or voltage characteristics of the PMOS transistors MP11 and MP12 is larger than the slope of a curve of current and/or voltage characteristics of the NMOS transistors MN11 and MN12. In this situation the transconductance gmp of the PMOS transistors is larger than the transconductance gmn of the NMOS transistors, and thus, the stability of the current sense amplifier circuit may deteriorate. Furthermore, as the power supply voltage increases, the stability of the current sense amplifier circuit continues to deteriorate, which may result in the inability to increase the amplification of an operation voltage. Consequently, the operation speed of a conventional current sense amplifier circuit may be slow and may be sensitive to noise.
Embodiments of the present invention provide a current sense amplifier including first and second sense transistors having cross-coupled gates and drains. The current sense amplifier further includes first and second load devices having first terminals connected to respective drains of the first and second sense transistors and a latch having first and second inputs connected to respective drains of the first and second sense transistors. The amplifier still further includes an enable device that is responsive to an enable signal and has a first terminal connected to second terminals of the first and second load devices and a first output of the latch.
In other embodiments of the present invention the first and second load devices may include first and second load transistors, respectively, that are connected as diodes. The latch may include first and second MOS transistors having crosscoupled drain and gates and may be responsive to a bias signal. The bias signal may be generated by a bias circuit that generates the bias signal on an output signal line in response to a control signal.
In further embodiments of the present invention, the bias circuit may include a first PMOS transistor having a source connected to a power supply voltage and a gate and a drain connected together. The circuit may further include a first NMOS transistor responsive to the control signal having a drain connected to the gate and drain of the first PMOS transistor and a source connected to the output signal line and second and third NMOS transistors connected in a totem pole arrangement between the output signal line and a ground voltage and having cross coupled gates and drains in a diode structure. The circuit may still further include a fourth NMOS transistor having a gate connected to the control signal, a drain connected to the output signal line and a source connected to the ground voltage.
In still further embodiments of the present invention, the control signal may be generated in response to a column selection signal and a latch instruction signal that indicates the time of the latch. The bias signal may be a logic high when the control signal is a logic low and the bias signal may be a logic low when the control signal is a logic high. The latch may be activated when the bias signal is at a logic high and may be deactivated when the bias signal is at a logic low. The control signal may be a logic low when a pair of first and second output voltages vary. The control signal may be a logic high when the first and second output signals are constant and have different values. The control signal may be a logic high when a power supply voltage is increased beyond a predetermined level.